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| 1/25 l6563 november 2004 this is preliminary information on a new product now in development or undergoing evaluation. details are subject to change wit hout notice. 1 main features transition-mode control of pfc pre- regulators very precise adjustable output overvoltage protection tracking boost function protection against feedback loop failure (latched shutdown) interface for cascaded conver- ter's pwm controller input voltage feedforward (1/v 2 ) remote on/off control low ( 90a) start-up current 5 ma max. quiescent current 1.5% (@ tj = 25c) internal reference voltage -600/+800 ma totem pole gate driver with active pull-down during uvlo so14 package 1.1 applications pfc pre-regulators for: hi-end ac-dc adapter/charger desktop pc, server, web server iec61000-3-2 or jeida-miti compliant smps, in excess of 250w 2description the device is a current-mode pfc controller oper- ating in transition mode (tm). based on the core of a standard tm pfc controller, it offers improved performance and additional functions. preliminary data advanced transition-mode pfc controller figure 2. block diagram + - v ref2 vbias (internal supply bus) + - 2.5v r1 r2 + - - + zero current detector v cc 14 123 4 zcd v cc inv comp mult cs gd 13 11 gnd 12 multiplier r s q starter 1.7v + - 6 tbo + - 2.5v pfc_ok 7 1:1 current mirror + - run 10 0.52v 0.62v pwm_latch 8 5 vff leading-edge blanking 1:1 buffer from vff 1.4v 0.7v pwm_stop 9 vbias uvlo comparator + - 0.2v 0.3v 15 v sat disable latch uvlo 3v sat ideal diode 1 / v 2 starter off driver q tracking boost on/off control (brownout detection) line voltage feedforward inductor saturation detection feedback failure detection voltage regulator voltage references rev. 1 fi gure 1. p ac k age table 1. order codes part number package l6563 so14 L6563TR so14 in tape & reel so14
l6563 2/25 2 description (continued) the highly linear multiplier, along with a special correction circuit that reduces crossover distortion of the mains current, allows wide-range-mains operation with an extremely low thd even over a large load range. the output voltage is controlled by means of a voltage-mode error amplifier and a precise (1.5% @t j = 25c) internal voltage reference. the stability of the loop and the transient response to sudden mains voltage changes are improved by the voltage feedforward function (1/v 2 correction). additionally, the ic provides the option for tracking boost operation (where the output voltage is changed tracking the mains voltage). the device features extremely low consumption ( 90 a before start-up and 5 ma running). an interface with the pwm controller of the dc-dc converter supplied by the pfc pre-regulator is provid- ed: the purpose is to stop the operation of the converter in case of anomalous conditions for the pfc stage (feedback loop failure, boost inductor's core saturation) and to disable the pfc stage in case of light load for the dc-dc converter, so as to make it easier to comply with energy saving norms (blue angel, ener- gystar, energy2000, etc.). the device includes disable functions suitable for remote on/off control both in systems where the pfc pre-regulator works as a master and in those where it works as a slave. in addition to an effective two-step ovp that handles normal operation overvoltages, the ic provides also a protection against feedback loop failures or erroneous output voltage setting. table 2. absolute maximum ratings table 3. thermal data figure 3. pin connection (top view) symbol pin parameter value unit vcc 14 ic supply voltage (icc = 20 ma) self-limited v --- 2, 4 to 6, 8 to 10 analog inputs & outputs -0.3 to 8 v --- 1, 3, 7 max. pin voltage (i pin =1 ma) self-limited v i pwm_stop 10 max. sink current 3 ma i zcd 11 zero current detector max. current -10 (source) 10 (sink) ma ptot power dissipation @tamb = 50c 0.75 w tj junction temperature operating range -25 to 150 c tstg storage temperature -55 to 150 c symbol parameter value unit r th j-amb thermal resistance, junction-to-ambient max. 120 c/w inv comp mult cs vff tbo pfc_ok vcc gd gnd zcd run pwm_stop pwm_latch 1 2 3 4 5 6 7 14 13 12 11 10 9 8 3/25 l6563 table 4. pin description pin # pin name function 1 inv inverting input of the error amplifier. the information on the output voltage of the pfc pre- regulator is fed into the pin through a resistor divider. the pin normally features high impedance but, if the tracking boost function is used, an inter- nal current generator programmed by tbo (pin #6) is activated. it sinks current from the pin to change the output voltage so that it tracks the mains voltage. 2 comp output of the error amplifier. a compensation network is placed between this pin and inv (pin #1) to achieve stability of the voltage control loop and ensure high power factor and low thd. 3 mult main input to the multiplier. this pin is connected to the rectified mains voltage via a resistor divider and provides the sinusoidal reference to the current loop. the voltage on this pin is used also to derive the information on the rms mains voltage. 4 cs input to the pwm comparator. the current flowing in the mosfet is sensed through a resis- tor, the resulting voltage is applied to this pin and compared with an internal reference to determine mosfet?s turn-off. a second comparison level at 1.7v detects abnormal currents (e.g. due to boost inductor sat- uration) and, on this occurrence, shuts down the ic, reduces its consumption almost to the start-up level and asserts pwm_latch (pin #8) high. 5vff second input to the multiplier for 1/v 2 function. a capacitor and a parallel resistor must be connected from the pin to gnd. they complete the internal peak-holding circuit that derives the information on the rms mains voltage. the voltage at this pin, a dc level equal to the peak voltage at pin mult (#3), compensates the control loop gain dependence on the mains voltage. never connect the pin directly to gnd. 6 tbo tracking boost function. this pin provides a buffered vff voltage. a resistor connected between this pin and gnd defines a current that is sunk from pin inv (#1). in this way, the output voltage is changed proportionally to the mains voltage (tracking boost). if this function is not used leave this pin open. 7 pfc_ok pfc pre-regulator output voltage monitoring/disable function. this pin senses the output volt- age of the pfc pre-regulator through a resistor divider and is used for protection purposes. if the voltage at the pin exceeds 2.5v the ic is shut down, its consumption goes almost to the start-up level and this condition is latched. pwm_latch pin is asserted high. normal opera- tion can be resumed only by cycling the vcc. this function is used for protection in case the feedback loop fails. if the voltage on this pin is brought below 0.2v the ic is shut down and its consumption is considerably reduced. to restart the ic the voltage on the pin must go above 0.26v. if these functions are not needed, tie the pin to a voltage between 0.26 and 2.5 v. 8 pwm_latch output pin for fault signaling. during normal operation this pin features high impedance. if either a voltage above 2.5v at pfc_ok (pin #7) or a voltage above 1.7v on cs (pin #4) is detected the pin is asserted high. normally, this pin is used to stop the operation of the dc- dc converter supplied by the pfc pre-regulator by invoking a latched disable of its pwm controller. if not used, the pin will be left floating. 9 pwm_stop output pin for fault signaling. during normal operation this pin features high impedance. if the ic is disabled by a voltage below 0.5v on run (pin #10) the voltage at the pin is pulled to ground. normally, this pin is used to temporarily stop the operation of the dc-dc converter supplied by the pfc pre-regulator by disabling its pwm controller. if not used, the pin will be left floating. 10 run remote on/off control. a voltage below 0.52v shuts down (not latched) the ic and brings its consumption to a considerably lower level. pwm_stop is asserted low. the ic restarts as the voltage at the pin goes above 0.6v. connect this pin to vff (pin #5) either directly or through a resistor divider to use this function as brownout (ac mains undervoltage) protec- tion, tie to inv (pin #1) if the function is not used. 11 zcd boost inductor?s demagnetization sensing input for transition-mode operation. a negative- going edge triggers mosfet?s turn-on. 12 gnd ground. current return for both the signal part of the ic and the gate driver. 13 gd gate driver output. the totem pole output stage is able to drive power mosfet?s and igbt?s with a peak current of 600 ma source and 800 ma sink. the high-level voltage of this pin is clamped at about 12v to avoid excessive gate voltages. 14 vcc supply voltage of both the signal part of the ic and the gate driver. l6563 4/25 figure 4. typical system block diagram table 5. electrical characteristcs (t j = -25 to 125c, v cc =12, c o = 1 nf between pin gd and gnd, c ff =1f between pin v ff and gnd; unless otherwise specified) symbol parameter test condition min. typ. max. unit supply voltage vcc operating range after turn-on 10.3 22 v vcc on turn-on threshold (1) 11 12 13 v vcc off turn-off threshold (1) 8.7 9.5 10.3 v hys hysteresis 2.3 2.7 v v z zener voltage icc = 20 ma 22 25 28 v supply current i start-up start-up current before turn-on, vcc=10v 50 90 a i q quiescent current after turn-on 3 5 ma i cc operating supply current @ 70 khz 3.8 5.5 ma i qdis idle state quiescent current latched by pfc_ok>vthl or vcs>v csdis 180 250 a disabled by pfc_ok l6563 6/25 (1), (2) parameters tracking each other (3) the multiplier output is given by: (4) parameters guaranteed by design, functionality tested in production. i inv -i tbo current mismatch i tbo = 25 a to 0.25 ma -3.5 3.5 % v tboclamp clamp voltage (2) v vff = 4v 2.9 3 3.1 v pfc_ok v thl latch-off threshold (2) voltage rising 2.4 2.5 2.6 v v th disable threshold (2) voltage falling 0.2 v v en enable threshold (2) voltage rising 0.26 v i pfc_ok input bias current v pfc_ok = 0 to 2.5v -0.1 -1 a v clamp clamp voltage i pfc_ok = 1 ma 9 9.5 v pwm_latch i leak low level leakage current v pwm_latch =0 -1 a v h high level i pwm_latch = -0.5 ma 3.7 v pwm_stop i leak high level leakage current v pwm_stop = 6v 1 a v l low level i pwm_stop = 0.5 ma 1 v v clamp clamp voltage i pfc_ok = 2 ma 9 9.5 v run function i run input bias current v run = 0 to 3 v -1 a v dis disable threshold (2) voltage falling 0.5 0.52 0.54 v v en enable threshold (2) voltage rising 0.57 0.6 0.63 v start timer t start start timer period 75 150 300 s gate driver v ohdrop dropout voltage i gdsource = 20 ma 2 2.6 v i gdsource = 200 ma 2.5 3 v v oldrop i gdsink = 200 ma 1 2 v t f current fall time 30 70 ns t r current rise time 40 80 ns v oclamp output clamp voltage i gdsource = 5ma; vcc = 20v 10 12 15 v uvlo saturation vcc=0 to vcc on , i sink =10ma 1.1 v table 5. electrical characteristcs (continued) (t j = -25 to 125c, v cc =12, c o = 1 nf between pin gd and gnd, c ff =1f between pin v ff and gnd; unless otherwise specified) symbol parameter test condition min. typ. max. unit v cs k m v mult v comp 2.5 ? () ? v vff 2 ----------------------------------------------------------- ? = 7/25 l6563 3 typical electrical performance figure 5. supply current vs. supply voltage figure 6. ic consumption vs. tj figure 7. start-up & uvlo vs. tj figure 8. vcc zener voltage vs. tj figure 9. feedback reference vs. tj figure 10. e/a output clamp levels vs. tj vcc(v) 0 0.005 0.01 0.05 0.1 0.5 1 5 10 icc (ma) 0 5 10 15 20 co = 1nf f = 70 khz t j = 25c 25 -50 0 50 100 150 0.02 0.05 0.1 0.2 0.5 1 2 5 10 icc (ma) operating quiescent disabled or during ovp before start-up vcc = 12 v co = 1 nf f = 70 khz tj (c) latched off tj (c) v cc-on (v) v cc-off (v) -50 0 50 100 150 9 9.5 10 10.5 11 11.5 12 12.5 tj (c) vcc z (pin 14) (v) -50 0 50 100 150 22 23 24 25 26 27 28 v ref (v) -50 0 50 100 150 2.4 2.45 2.5 2.55 2.6 vcc = 12 v tj (c) (pin 1) tj (c) v comp (pin 2) (v) -50 0 50 100 150 1 2 3 4 5 6 7 upper clamp lower clamp vcc = 12 v l6563 8/25 figure 11. static ovp level vs. tj figure 12. dynamic ovp current vs. tj (normalized value) figure 13. delay-to-output vs. tj figure 14. vcs clamp vs. tj figure 15. current-sense offset vs. mains voltage phase angle figure 16. ic disable level on current sense vs. tj tj (c) v comp (pin 2) (v) -50 0 50 100 150 2 2.1 2.2 2.3 2.4 2.5 vcc = 12 v i ovp -50 0 50 100 150 80% 90% 100% 110% 120% vcc = 12 v tj (c) tj (c) t d(h-l) (ns) -50 0 50 100 150 50 100 150 200 250 300 vcc = 12 v tj (c) v csx (pin 4) (v) -50 0 50 100 150 1 1.1 1.2 1.3 1.4 1.5 vcc = 12 v v comp = upper clamp ( ) v csoffset (pin 4) (mv) 0 0.628 1.256 1.884 2.512 3.14 0 5 10 15 20 25 30 vcc = 12 v tj = 25 v mult = 0 to 3v v ff = 3v v mult = 0 to 0.7v v ff = 0.7v tj (c) vpin4 (v) -50 0 50 100 150 1.0 1.2 1.4 1.6 1.8 2.0 vcc = 12 v 9/25 l6563 figure 17. multiplier characteristics @ vff=1v figure 18. multiplier characteristics @ vff=3v figure 19. multiplier gain vs. tj figure 20. zcd clamp levels vs. tj figure 21. zcd source capability vs. tj figure 22. vff & tbo dropouts vs. tj v mult (pin 3) (v) v comp (pin 2) (v) 0 0.2 0.4 0.6 0.8 1 1.2 0 0.2 0.4 0.6 0.8 1 2.6 3.0 3.5 4.0 4.5 upper voltage clamp 5.0 5.5 v cs (pin 4) (v) vcc = 12 v tj = 25 c v mult (pin 3) (v) v comp (pin 2) (v) 00.511.522.533.5 0 0.1 0.2 0.3 0.4 0.5 2.6 3.0 3.5 4.0 4.5 upper voltage clamp 5.0 5.5 v cs (pin 4) (v) vcc = 12 v tj = 25 c k m tj (c) -50 0 50 100 150 0 0.2 0.4 0.6 0.8 1 vcc = 12 v v comp =4 v v mult = v ff =1v tj (c) v zcd (pin 11) (v) -50 0 50 100 150 -1 0 1 2 3 4 5 6 7 vcc = 12 v i zcd = 2.5 ma upper clamp lower clamp tj (c) i zcdsrc (ma) -50 0 50 100 150 -8 -6 -4 -2 0 vcc = 12 v v zcd = lower clamp tj (c) -50 0 50 100 150 -2 0 2 4 6 (mv) vpin5 - vpin3 vpin6 - vpin5 vcc = 12 v vpin3 = 2.9 v l6563 10/25 figure 23. tbo current mismatch vs. tj figure 24. tbo-inv current mismatch vs. tbo currents figure 25. tbo clamp vs. tj figure 26. run thresholds vs. tj figure 27. pwm_latch high saturation vs. tj figure 28. pwm_stop low saturation vs. tj tj (c) -50 0 50 100 150 -2.4 -2.2 -2.0 -1.8 -1.6 -1.4 -1.2 -1.0 -0.8 i(inv)-i(tbo) i(inv) 100 itbo = 25 a itbo = 250 a vcc = 12 v i(tbo) 0 100 200 300 400 500 600 -2.3 -2.2 -2.1 -2.0 -1.9 -1.8 -1.7 -1.6 vcc = 12 v tj = 25 c i(inv)-i(tbo) i(inv) 100 tj (c) -50 0 50 100 150 2.5 2.75 3 3.25 3.5 vcc = 12 v vpin3= 4 v (v) vpin6 tj (c) -50 0 50 100 150 2.5 2.75 3 3.25 3.5 vcc = 12 v vpin3= 4 v (v) vpin6 tj (c) vpin10 (v) -50 0 50 100 150 0.0 0.2 0.4 0.6 0.8 1.0 vcc = 12 v on off tj (c) vpin10 (v) -50 0 50 100 150 0.0 0.2 0.4 0.6 0.8 1.0 vcc = 12 v on off tj (c) vpin8 (v) -50 0 50 100 150 4.5 4.6 4.7 4.8 4.9 5.0 5.1 5.2 5.3 vcc = 12 v isource = 50 a isource = 500 a tj (c) vpin8 (v) -50 0 50 100 150 4.5 4.6 4.7 4.8 4.9 5.0 5.1 5.2 5.3 vcc = 12 v isource = 50 a isource = 500 a tj (c) vpin9 (v) -50 0 50 100 150 0.0 1.0 2.0 3.0 4.0 5.0 vcc = 12 v isink = 0.5 ma 0.50 0.40 0.30 0.20 0.10 0 tj (c) vpin9 (v) -50 0 50 100 150 0.0 1.0 2.0 3.0 4.0 5.0 vcc = 12 v isink = 0.5 ma 0.50 0.40 0.30 0.20 0.10 0 11/25 l6563 figure 29. pfc_ok thresholds vs. tj figure 30. start-up timer vs. tj figure 31. gate-drive clamp vs. tj figure 32. uvlo saturation vs. tj figure 33. gate-drive output low saturation figure 34. gate-drive output high saturation tj (c) vpin7 (v) -50 0 50 100 150 0.1 0.2 0.3 0.5 1.0 2.0 3.0 vcc = 12 v on off latch-off tj (c) vpin7 (v) -50 0 50 100 150 0.1 0.2 0.3 0.5 1.0 2.0 3.0 vcc = 12 v on off latch-off tj (c) tstart (s) -50 0 50 100 150 100 110 120 130 140 150 vcc = 12 v tj (c) tstart (s) -50 0 50 100 150 100 110 120 130 140 150 vcc = 12 v tj (c) vpin15 clamp (v) -50 0 50 100 150 10 10.5 11 11.5 12 vcc = 20 v tj (c) -50 0 50 100 150 0.5 0.6 0.7 0.8 0.9 1 1.1 vcc = 0 v vpin15 (v) v pin15 (v) 0 200 400 600 800 1,000 0 1 2 3 4 i gd (ma) tj = 25 c vcc = 11 v sink 0 100 200 300 400 500 600 700 -4.5 -4 -3.5 -3 -2.5 -2 -1.5 i gd (ma) tj = 25 c vcc = 11 v source vcc - 2.0 vcc - 2.5 vcc - 3.0 vcc - 3.5 vcc - 4.0 v pin15 (v) l6563 12/25 4 application information 4.1 overvoltage protection normally, the voltage control loop keeps the output voltage vo of the pfc pre-regulator close to its nominal value, set by the ratio of the resistors r1 and r2 of the output divider. neglecting the ripple components, under steady state conditions the current through r1 equals that through r2. considering that the non-in- verting input of the error amplifier is internally biased at 2.5v, the voltage at pin inv will be 2.5v as well, then: . if the output voltage experiences an abrupt change ? vo the voltage at pin inv is kept at 2.5v by the local feedback of the error amplifier, a network connected between pins inv and comp that introduces a long time constant. then the current through r2 remains equal to 2.5/r2 but that through r1 becomes: . the difference current ? i r1 = i? r1 - i? r1 = ? v o /r1 will flow through the compensation network and enter the error amplifier (pin comp). this current is monitored inside the ic and when it reaches about 18 a the out- put voltage of the multiplier is forced to decrease, thus reducing the energy drawn from the mains. if the cur- rent exceeds 20 a, the ovp is triggered (dynamic ovp), and the external power transistor is switched off until the current falls approximately below 5 a. however, if the overvoltage persists (e.g. in case the load is completely disconnected), the error amplifier will eventually saturate low hence triggering an internal com- parator (static ovp) that will keep the external power switch turned off until the output voltage comes back close to the regulated value. the output overvoltage that is able to trigger the ovp function is then: ? v o = r1 20 10 -6 an important advantage of this technique is that the overvoltage level can be set independently of the reg- ulated output voltage: the latter depends on the ratio of r1 to r2, the former on the individual value of r1. another advantage is the precision: the tolerance of the detection current is 15%, which means 15% tol- erance on the ? vo. since it is usually much smaller than vo, the tolerance on the absolute value will be proportionally reduced. example: vo=400v, ? vo=40v. then: r1=40v/20a=2m ? ; r2=2.52m ? /(400-2.5)=12.58k ? . the toler- ance on the ovp level due to the l6563 will be 400.15=6 v, that is 1.36%. when either ovp is activated the quiescent consumption is reduced to minimize the discharge of the vcc capacitor. figure 35. output voltage setting, ovp and ffp functions: internal block diagram i r2 i r1 2.5 r2 ------- - v o 2.5 ? r1 --------------------- - === i ' r1 v o 2.5 ? v o ? + r1 --------------------------------------- - = - + 2.5v l6563 1 2 inv comp e/a + - frequency compensation + - r2 7 pfc_ok i tbo - + 2.25v static ovp - + dynamic ovp 20 a vout { r1a r1b r1 9.5v fault (latched) tbo function r4 { r3a r3b r3 + - fault (not latched) 0.26v 9.5v 13/25 l6563 4.2 feedback failure protection (ffp) the ovp function above described is able to handle "normal" overvoltage conditions, i.e. those resulting from an abrupt load/line change or occurring at start-up. it cannot handle the overvoltage generated, for instance, when the upper resistor of the output divider (r1) fails open: the voltage loop can no longer read the information on the output voltage and will force the pfc pre-regulator to work at maximum on-time, causing the output voltage to rise with no control. a pin of the device (pfc_ok) has been dedicated to provide an additional monitoring of the output voltage with a separate resistor divider (r3 high, r4 low, see figure 35 ). this divider is selected so that the voltage at the pin reaches 2.5v if the output voltage exceeds a preset value, usually larger than the maximum vo that can be expected, also including worst-case load/line transients. example: vo = 400 v, vox = 475 v. select: r3=3m ? ; then: r4=3m ? 2.5/(475-2.5)=15.87k ? . when this function is triggered, the gate drive activity is immediately stopped, the device is shut down, its quiescent consumption is reduced below 250 a and the condition is latched as long as the supply voltage of the ic is above the uvlo threshold. at the same time the pin pwm_latch is asserted high. pwm_latch is an open source output able to deliver 3.7v min. with 0.5 ma load, intended for tripping a latched shutdown function of the pwm controller ic in the cascaded dc-dc converter, so that the entire unit is latched off. to restart the system it is necessary to recycle the input power, so that the vcc voltages of both the l6563 and the pwm controller go below their respective uvlo thresholds. the pfc_ok pin doubles its function as a not-latched ic disable: a voltage below 0.2v will shut down the ic, reducing its consumption below 1 ma. in this case both pwm_stop and pwm_latch keep their high impedance status. to restart the ic simply let the voltage at the pin go above 0.26 v. note that this function offers a complete protection against not only feedback loop failures or erroneous settings, but also against a failure of the protection itself. either resistor of the pfc_ok divider failing short or open or a pfc_ok pin floating will result in shutting down the ic and stopping the pre-regulator. 4.3 voltage feedforward the power stage gain of pfc pre-regulators varies with the square of the rms input voltage. so does the crossover frequency f c of the overall open-loop gain because the gain has a single pole characteristic. this leads to large trade-offs in the design. for example, setting the gain of the error amplifier to get f c = 20 hz @ 264 vac means having f c ? 4 hz @ 88 vac, resulting in a sluggish control dynamics. additionally, the slow control loop causes large transient current flow during rapid line or load changes that are limited by the dynamics of the multiplier output. this limit is considered when selecting the sense resistor to let the full load power pass under minimum line voltage conditions, with some margin. but a fixed current limit allows excessive power input at high line, whereas a fixed power limit requires the current limit to vary inversely with the line voltage. voltage feedforward can compensate for the gain variation with the line voltage and allow overcoming all of the above-mentioned issues. it consists of deriving a voltage proportional to the input rms voltage, feeding this voltage into a squarer/divider circuit (1/v 2 corrector) and providing the resulting signal to the multiplier that generates the current reference for the inner current control loop (see figure 36 ). figure 36. voltage feedforward: squarer-divider (1/v 2 ) block diagram and transfer characteristic 01234 0 0.5 1 1.5 2 v ff =v mult vcsx 0.5 v comp =4v actual ideal 5 mult 3 r5 rectified mains r6 "ideal" diode current reference (vcsx) 9.5v vff c ff r ff e/a output (v comp ) - + 1/v 2 multiplier l6563 l6563 14/25 in this way a change of the line voltage will cause an inversely proportional change of the half sine ampli- tude at the output of the multiplier (if the line voltage doubles the amplitude of the multiplier output will be halved and vice versa) so that the current reference is adapted to the new operating conditions with (ide- ally) no need for invoking the slow dynamics of the error amplifier. additionally, the loop gain will be con- stant throughout the input voltage range, which improves significantly dynamic behavior at low line and simplifies loop design. actually, deriving a voltage proportional to the rms line voltage implies a form of integration, which has its own time constant. if it is too small the voltage generated will be affected by a considerable amount of ripple at twice the mains frequency that will cause distortion of the current reference (resulting in high thd and poor pf); if it is too large there will be a considerable delay in setting the right amount of feedforward, resulting in excessive overshoot and undershoot of the pre-regulator's output voltage in response to large line voltage changes. clearly a trade-off is required. the l6563 realizes voltage feedforward with a technique that makes use of just two external parts and that limits the feedforward time constant trade-off issue to only one direction. a capacitor c ff and a resis- tor r ff , both connected from the vff (#5) pin to ground, complete an internal peak-holding circuit that provides a dc voltage equal to the peak of the rectified sine wave applied on pin mult (#3). r ff provides a means to discharge c ff when the line voltage decreases (see figure 36 ). in this way, in case of sudden line voltage rise, c ff will be rapidly charged through the low impedance of the internal diode and no ap- preciable overshoot will be visible at the pre-regulator's output; in case of line voltage drop c ff will be dis- charged with the time constant r ff c ff , which can be in the hundred ms to achieve an acceptably low steady-state ripple and have low current distortion; consequently the output voltage can experience a con- siderable undershoot, like in systems with no feedforward compensation. the twice-mains-frequency (2f l ) ripple appearing across c ff is triangular with a peak-to-peak amplitude that, with good approximation, is given by: , where f l is the line frequency. the amount of 3 rd harmonic distortion introduced by this ripple, related to the amplitude of its 2f l component, will be: figure 37 shows a diagram that helps choose the time constant r ff c ff based on the amount of maxi- mum desired 3 rd harmonic distortion. always connect r ff and c ff to the pin, the ic will not work properly if the pin is either left floating or connected directly to ground. figure 37. r ff c ff as a function of 3 rd harmonic distortion introduced in the input current the dynamics of the voltage feedforward input is limited downwards at 0.5v (see figure 36 ), that is the output of the multiplier will not increase any more if the voltage on the v ff pin is below 0.5v. this helps to prevent excessive power flow when the line voltage is lower than the minimum specified value v ff ? 2v multpk 14f l r ff c ff + ---------------------------------------- = d 3 % 100 2 f l r ff c ff ---------------------------------- = d % 3 0.1 1 10 0.01 0.1 1 10 f = 50 hz l f = 60 hz l r c [s] ff ff 15/25 l6563 4.4 thd optimizer circuit the l6563 is provided with a special circuit that reduces the conduction dead-angle occurring to the ac input current near the zero-crossings of the line voltage (crossover distortion). in this way the thd (total harmonic distortion) of the current is considerably reduced. a major cause of this distortion is the inability of the system to transfer energy effectively when the instan- taneous line voltage is very low. this effect is magnified by the high-frequency filter capacitor placed after the bridge rectifier, which retains some residual voltage that causes the diodes of the bridge rectifier to be reverse-biased and the input current flow to temporarily stop. to overcome this issue the device forces the pfc pre-regulator to process more energy near the line volt- age zero-crossings as compared to that commanded by the control loop. this will result in both minimizing the time interval where energy transfer is lacking and fully discharging the high-frequency filter capacitor after the bridge. figure 38. thd optimization: standard tm pfc controller (left side) and l6563 (right side) essentially, the circuit artificially increases the on-time of the power switch with a positive offset added to the output of the multiplier in the proximity of the line voltage zero-crossings. this offset is reduced as the instantaneous line voltage increases, so that it becomes negligible as the line voltage moves toward the top of the sinusoid. furthermore the offset is modulated by the voltage on the v ff pin (see voltage feed- forward section) so as to have little offset at low line, where energy transfer at zero crossings is typically quite good, and a larger offset at high line where the energy transfer gets worse. the effect of the circuit is shown in figure 38 , where the key waveforms of a standard tm pfc controller are compared to those of this chip. to take maximum benefit from the thd optimizer circuit, the high-frequency filter capacitor after the bridge rectifier should be minimized, compatibly with emi filtering needs. a large capacitance, in fact, introduces a conduction dead-angle of the ac input current in itself - even with an ideal energy transfer by the pfc pre-regulator - thus reducing the effectiveness of the optimizer circuit. imains vdrain imains vdrain input current input current mosfet's drain voltage mosfet's drain voltage rectified mains voltage rectified mains voltage input current input current l6563 16/25 4.5 tracking boost function in some applications it may be advantageous to regulate the output voltage of the pfc pre-regulator so that it tracks the rms input voltage rather than at a fixed value like in conventional boost pre-regulators. this is commonly referred to as "tracking boost" or "follower boost" approach. with the l6563 this can be realized by connecting a resistor (r t ) between the tbo pin and ground. the tbo pin presents a dc level equal to the peak of the mult pin voltage and is then representative of the mains rms voltage. the resistor defines a current, equal to v(tbo)/r t , that is internally 1:1 mirrored and sunk from pin inv (#1) input of the l6563's error amplifier. in this way, when the mains voltage increases the voltage at tbo pin will increase as well and so will do the current flowing through the resistor connect- ed between tbo and gnd. then a larger current will be sunk by inv pin and the output voltage of the pfc pre-regulator will be forced to get higher. obviously, the output voltage will move in the opposite di- rection if the input voltage decreases. to avoid undesired output voltage rise should the mains voltage exceed the maximum specified value, the voltage at the tbo pin is clamped at 3v. by properly selecting the multiplier bias it is possible to set the maximum input voltage above which input-to-output tracking ends and the output voltage becomes con- stant. if this function is not used, leave the pin open: the device will regulate a fixed output voltage. starting from the following data: vin 1 = minimum specified input rms voltage; vin 2 = maximum specified input rms voltage; vo 1 = regulated output voltage @ vin = vin1; vo 2 = regulated output voltage @ vin = vin2; vox = absolute maximum limit for the regulated output voltage; ? vo = ovp threshold, to set the output voltage at the desired values use the following design procedure: 1) determine the input rms voltage vin clamp that produces vo = vox: and choose a value vin x such that vin 2 = vin x < vin clamp . this will result in a limitation of the output volt- age range below vox (it will equal vox if one chooses vin x = vin clamp ) 2) determine the divider ratio of the mult pin (#3) bias: and check that at minimum mains voltage vin 1 the peak voltage on pin 3 is greater than 0.65v. 3) determine r1, the upper resistor of the output divider: . 4) calculate the lower resistor r2 of the output divider and the adjustment resistor r t : . 5) check that the maximum current sourced by the tbo pin (#6) does not exceed the maximum specified (0.25 ma): . in the following mathcad? sheet, as an example, the calculation is shown for the circuit illustrated in figure 39. figure 40 shows the internal block diagram of the tracking boost function. vin clamp vox vo 1 ? vo 2 vo 1 ? --------------------------- - vin 2 vox vo 2 ? vo 2 vo 1 ? --------------------------- - vin 1 ? ? ? = k 3 2vin x ? ----------------------- - = r1 vo ? 20 ---------- - 10 6 ? = r2 2.5 r1 vin 2 vin 1 ? vo 1 2.5 ? () vin 2 vo 2 2.5 ? () vin 1 ? ? ? --------------------------------------------------------------------------------------------------- ? ? = r t 2kr1 vin 2 vin 1 ? vo 2 vo 1 ? ------------------------------ - ?? ? = ? ? ? ? ? ? ? i tbomax 3 r t ------ - 0.25 10 3 ? ? = 17/25 l6563 design data vin 1 :=88v vo 1 := 200v vin 2 :=264v vo 2 := 385v vox;=400v ? vo;=40v step 1 vin clamp = 278.27v choose: vin x : = 270v step 2 k = 7.857 x 10 -3 step 3 r1 = 2 x 10 6 ? step 4 r2 = 4.762 x 10 4 ? r t = 2.114 x 10 4 ? step 5 i tbomax = 0.142 ma vo(vi): = vo(vin 1 ) = 200 v vo(vin 2 ) = 385 v vo(vin x ) = 391.307 v vin clamp : vox vo 1 ? vo 2 vo 1 ? --------------------------- - vin 2 ? = vox vo 2 ? vo 2 vo 1 ? --------------------------- - vin 1 ? ? k: 3 2vin x ? ----------------------- - = r1: vo ? 20 ---------- - 10 6 ? = r2: 2.5 r1 vin 2 vin 1 ? vo 1 2.5 ? () vin 2 vo 2 2.5 ? () vin 1 ? ? ? --------------------------------------------------------------------------------------------------- ? ? = r t :k2r1 vin 2 vin 1 ? vo 2 vo 1 ? ------------------------------ - ?? ? = i tbomax : 3 r t ------- 10 3 ? = v multpk k2vi ?? v tbo if v multpk 3,v multpk ,3 < () 2.5 1 r1 r2 ------- - + ?? ?? v tbo r1 r t ------- - ? + ? 100 150 200 250 300 200 250 300 350 400 vo 2 vo vin () vin 2 vin x vin vox l6563 18/25 figure 39. 80w, wide-range-mains pfc pre-regulator with tracking boost function active figure 40. tracking boost and voltage feedforward blocks 4.6 inductor saturation detection boost inductor's hard saturation may be a fatal event for a pfc pre-regulator: the current upslope be- comes so large (50-100 times steeper, see figure 41 ) that during the current sense propagation delay the current may reach abnormally high values. the voltage drop caused by this abnormal current on the sense resistor reduces the gate-to-source voltage, so that the mosfet may work in the active region and dis- sipate a huge amount of power, which leads to a catastrophic failure after few switching cycles. a well-designed boost inductor must not saturate even under the worst-case operating conditions, that is at power-up with maximum load and minimum line voltage, when the error amplifier saturates high and commands the maximum peak current (defined by the current reference clamp, v csclamp , and the sense resistor) for some line cycles. however, especially in the development stage, inductor saturation may be encountered and a protection able to prevent the application from blowing up can be very useful. the device is provided with a second comparator on the current sense pin (cs, #4) that stops and latches off the ic if the voltage on the pin, normally limited within 1.1v, exceeds 1.7v. also the cascaded dc-dc converter can be stopped via the pwm_latch pin that is asserted high. in this way there can be abnor- mal current only for one cycle, after that the system is stopped and enabled to restart only after recycling the input power, that is when the vcc voltages of the ic and the pwm controller go below their respective uvlo thresholds. system safety will be considerably increased. 14 3 bridge 4 x 1n4007 c1 0.22 f 400v c3 22 f 25v fuse 4a/250v r3 68 k ? t 11 12 l6563 13 21 c6 100 nf r6 10 ? mos stp8nm50 4 c6 56 f 400v vo=200 to 385 v po=80w vac (88v to 264v) r7a,b 0.68 ? 1/4 w r9 47.5 k ? + - c2 2.2nf d1 stth1l06 ntc r5 62 k ? c5 1 f 5 c4 470 nf 6 7 10 8 9 r4 21 k ? r8b 1 m ? supply voltage 10.3 to 22v r8a 1 m ? c7 10 nf r10b 3.3 m ? r10a 3.3 m ? r11 34.8 k ? r1b 3.3 m ? r1a 3.3 m ? r2 51.1 k ? r10 390 k ? r1 l6563 inv 1 vout tbo 6 1:1 current mirror r t 2.5v e/a + - comp 2 3v - + 5 i tbo i r1 mult 3 r5 rectified mains r6 "ideal" diode multiplier 1/v 2 current reference r2 i r2 i tbo 9.5v 9.5v vff c ff r ff 19/25 l6563 figure 41. effect of boost inductor saturation on the mosfet current and detection method 4.7 power management/housekeeping functions a special feature of this ic is that it facilitates the implementation of the "housekeeping" circuitry needed to coordinate the operation of the pfc stage to that of the cascaded dc-dc converter. the functions re- alized by the housekeeping circuitry ensure that transient conditions like power-up or power down se- quencing or failures of either power stage be properly handled. this device provides some pins to do that. as already mentioned, one communication line between the ic and the pwm controller of the cascaded dc-dc converter is the pwm_latch pin, which is normally open when the pfc works properly and goes high if it loses control of the output voltage (because of a failure of the control loop) or if the boost inductor saturates, with the aim of latching off the pwm controller of the cascaded dc-dc converter as well ( feedback failure protection (ffp) for more details ). a second communication line can be established via the disable function included in the pfc_ok pin ( feedback failure protection (ffp) for more details ). typically this line is used to allow the pwm con- troller of the cascaded dc-dc converter to shut down the l6563 in case of light load, to minimize the no- load input consumption. should the residual consumption of the chip be an issue, it is also possible to cut down the supply voltage. interface circuits like those shown in figure 42 , where the l6563 works along with the l5991, pwm controller with standby function, can be used. needless to say, this operation as- sumes that the cascaded dc-dc converter stage works as the master and the pfc stage as the slave or, in other words, that the dc-dc stage starts first, it powers both controllers and enables/disables the op- eration of the pfc stage. figure 42. interface circuits that let the l5991/ l5991a disable the l6563 at light load (slave pfc) the third communication line is the pwm_stop pin (#9), which works in conjunction with the run pin (#10). the purpose of the pwm_stop pin is to inhibit the pwm activity of both the pfc stage and the cascaded dc-dc converter. the pin is an open collector, normally open, that goes low if the device is disabled by a voltage lower than 0.52v on the run pin. it is important to point out that this function works correctly in systems where the pfc stage is the master and the cascaded dc-dc converter is the slave or, in other words, where the pfc stage starts first, powers both controllers and enables/disables the op- t delay ? i l multiplier output vcs t 1.7v t delay multiplier output vcs t ? i l 1.7v t delay multiplier output vcs t ? i l 1.7v inductor not saturating inductor slightly saturating inductor saturating hard l5991/a st-by 4 16 27 k ? vref l6563 pfc_ok 7 100 k ? 150 k ? 150 k ? 47 k ? 100 nf bc547 bc547 bc557 l5991/a st-by 4 16 27 k ? vref l6563 vcc 14 100 k ? 150 k ? 150 k ? 15 k ? 100 nf bc557 bc547 bc557 100 nf supply_bus l6563 20/25 eration of the dc-dc stage. this function is quite flexible and can be used in different ways. in systems comprising an auxiliary con- verter and a main converter (e.g. desktop pc's silver box or hi-end lcd-tv), where the auxiliary converter also powers the controllers of the main converter, the pin run can be used to start and stop the main converter. in the simplest case, to enable/disable the pwm controller the pwm_stop pin can be con- nected to either the output of the error amplifier ( figure 43 a ) or, if the chip is provided with it, to its soft- start pin ( figure 43 b ). the use of the soft-start pin allows the designer to delay the start-up of the dc-dc stage with respect to that of the pfc stage, which is often desired. an underlying assumption in order for that to work properly is that the uvlo thresholds of the pwm controller are certainly higher than those of the l6563. figure 43. interface circuits that let the l6563 switch on or off a pwm controller (master pfc) if this is not the case or it is not possible to achieve a start-up delay long enough (because this prevents the dc-dc stage from starting up correctly) or, simply, the pwm controller is devoid of soft start, the ar- rangement of figure 44 lets the dc-dc converter start-up when the voltage generated by the pfc stage reaches a preset value. the technique relies on the uvlo thresholds of the pwm controller. figure 44. interface circuits for actual power-up sequencing (master pfc) another possible use of the run and pwm_stop pins (again, in systems where the pfc stage is the master) is brownout protection, thanks to the hysteresis provided. brownout protection is basically a not-latched device shutdown function that must be activated when a condition of mains undervoltage is detected. this condition may cause overheating of the primary power section due to an excess of rms current. brownout can also cause the pfc pre-regulator to work open loop and this could be dangerous to the pfc stage itself and the downstream converter, should the input voltage return abruptly to its rated value. another problem is the spurious restarts that may occur during converter power down and that cause the output voltage of the converter not to decay to zero monotoni- cally. for these reasons it is usually preferable to shutdown the unit in case of brownout. a) b) l6563 10 9 off on pwm controller x l5991/a: x=6 uc284x: x=1 uc384x: x=1 l6565: x=2 run pwm_stop c ss l6563 off on l5991/a 7 ss 10 9 run pwm_stop supply rail 10 k ? bc558c bc337 vz1 l6563 10 off on 14 9 7 pwm controller l5991/a: x=8+9 uc284x: x=7 uc384x: x=7 l6565: x=8 l6598: x=12 x run vcc pwm_stop pfc_ok hv bus vz2 vz1 < uvlo, vz2 < 9 v vz1 + vz2 < vccmax 21/25 l6563 ic shutdown upon brownout can be easily realized as shown in figure 45. the scheme on the left is of general use, the one on the right can be used if the bias levels of the multiplier and the r ff c ff time con- stant are compatible with the specified brownout level and with the specified holdup time respectively. in table 6 it is possible to find a summary of all of the above mentioned working conditions that cause the device to stop operating. figure 45. brownout protection (master pfc) table 6. summary of l6563 idle states 5 application examples and ideas figure 46. 250w, wide-range-mains pfc pre-regulator with fixed output voltage condition caused or revealed by pwm_latch (pin 8) pwm_stop (pin9) typical ic consumption ic behavior uvlo vcc < 8.7 v open open 50 a auto-restart feedback disconnected pfc_ok > 2.5 v active (high) open 180 a latched saturated boost inductor vcs > 1.7 v active (high) open 180 a latched ac brownout run < 0.52 v open active (low) 1.5 ma auto-restart standby pfc_ok < 0.2 v open open 1.5 ma auto-restart 10 run ac mains l6563 vff l6563 5 run 10 r ff c ff 14 3 b1 kbu8m r1a 820 k ? c1 1 f 400v c2 1 f fuse 8a/250v r3 47 k ? 11 12 l6563 13 21 m1 stp12nm50 4 r9a 1 m ? c8 150 f 450 v vout = 400v pout = 250 w vac 88v to 264v r8a,b 0.22 ? 1 w r10 12.7 k ? + - c3 10nf d2 stth5l06 r6 33 ? c4 1 f r1b 820 k ? r2 10 k ? d3 1n4148 r9b 1 m ? ntc1 2.5 ? d1 1n5406 c6 470 nf 630 v r5 6.8 k ? l1 r4 1 m ? vcc 10.3 to 22 v r11a 1.87 m ? r12 20 k ? r11b 1.87 m ? 6 7 5 r7 390 k ? c5 470nf 8 9 c7 10 nf 10 boost inductor (l1) spec etd29x16x10 core, 3c85 ferrite or equivalent 1.5 mm gap for 150 h primary inductance primary: 74 turns 20xawg30 ( ? 0.3 mm) secondar y : 8 turns 0.1 mm l6563 22/25 figure 47. 350w, wide-range-mains pfc pre-regulator with fixed output voltage and fot control 14 3 b1 kbu8m r1a 620 k ? c1 1 f 400v c2 1 f fuse 8a/250v r8 1.5 k ? 11 12 l6563 13 21 m1a stp12nm50 4 c11 220 f 450 v vout = 400v pout = 350w vac 88v to 264v r12a,b,c 0.33 ? 1 w + - c3 10nf d2 stth806dti r9 6.8 ? c5 1 f r1b 620 k ? r2 10 k ? d3 1n4148 d5 1n4148 r7 12 k ? c7 560 pf c6 330 pf ntc1 2.5 ? d1 1n5406 c9 470 nf 630 v r5 6.8 k ? r10 6.8 ? d4 1n4148 m1b stp12nm50 r6 1.5 k ? tr1 bc557 l1 r15a 1.87 m ? r16 20 k ? r15b 1.87 m ? 6 7 5 r3 390 k ? c4 470nf 9 8 9 c10 10 nf 10 c8 330 pf r11 330 ? r13a 1 m ? r14 12.7 k ? r13b 1 m ? r4 1 m ? vcc 10.3 to 22 v l1: core e42*21*15, b2 material 1.9 mm air gap on centre leg, main winding inductance 0.55 mh 58 t of 20 x awg32 ( ? 0.2 mm) 23/25 l6563 6 package information figure 48. so14 mechanical data & package dimensions outline and mechanical data dim. mm inch min. typ. max. min. typ. max. a 1.35 1.75 0.053 0.069 a1 0.10 0.30 0.004 0.012 a2 1.10 1.65 0.043 0.065 b 0.33 0.51 0.013 0.020 c 0.19 0.25 0.007 0.01 d (1) 8.55 8.75 0.337 0.344 e 3.80 4.0 0.150 0.157 e 1.27 0.050 h 5.8 6.20 0.228 0.244 h 0.25 0.50 0.01 0.02 l 0.40 1.27 0.016 0.050 k 0? (min.), 8? (max.) ddd 0.10 0.004 (1) ?d? dimension does not include mold flash, protusions or gate burrs. mold flash, protusions or gate burrs shall not exceed 0.15mm per side. so14 0016019 d l6563 24/25 7 revision history table 7. revision history date revision description of changes november 2004 1 first issue information furnished is believed to be accurate and reliable. however, stmicroelectronics assumes no responsibility for the co nsequences of use of such information nor for any infringement of patents or other rights of third parties which may result from its use. no license is granted by implication or otherwise under any patent or patent rights of stmicroelectronics. specifications mentioned in this publicati on are subject to change without notice. this publication supersedes and replaces all information previously supplied. stmicroelectronics prod ucts are not authorized for use as critical components in life support devices or systems without express written approval of stmicroelectro nics. the st logo is a registered trademark of stmicroelectronics. all other names are the property of their respective owners ? 2004 stmicroelectronics - all rights reserved stmicroelectronics group of companies australia - belgium - brazil - canada - china - czech republic - finland - france - germany - hong kong - india - israel - ital y - japan - malaysia - malta - morocco - singapore - spain - sweden - switzerland - united kingdom - united states of america www.st.com 25/25 l6563 |
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